Globally Asynchronous Locally Synchronous, GALS, VLSI, Asynchronous Wrappers, Arbiter, Local Clock, AFSM


Globally-Asynchronous, Locally-Synchronous (GALS) design techniques employ the finer points of synchronous and asynchronous design methods to eliminate problems arising due to clock distribution, power dissipation, and large area over head. With the recent rise in the demand for System-on-a-Chip (SoC) designs, global clock distribution and power dissipation due to clock distribution are inevitable. In order to reduce/eliminate the effects of the global clock in synchronous designs and large area overhead in asynchronous designs, an alternative approach would be to utilize GALS design techniques. Not only do GALS designs eliminate the issue of using a global clock, they also have smaller area overhead when compared to purely asynchronous designs. Among the various GALS design approaches proposed till date, this thesis focuses on the working and implementation of Asynchronous Wrapper designs proposed by Muttersbach et al., in [1, 2]. This thesis specifically addresses different approaches to incorporate the wrappers in VLSI circuits, rather than discussing the efficiency and viability of GALS design techniques over purely synchronous or asynchronous approaches. It has been proven by researchers [3] that GALS design approaches bring down power consumption due to the elimination of the global clock by small amounts, but there is also a drop in performance. Since the goal of this thesis is to introduce the reader to GALS design techniques and not prove their efficiency, it is out of the scope of this thesis to validate the results shown in [3]. In our aim to introduce the reader to GALS design techniques, we first provide a comparison of synchronous and asynchronous design approaches, and then discuss the need for GALS design approaches. We will then address issues affecting GALS such as metastability, latency, flow control, and local clock alteration. After familiarizing the reader with the issues affecting GALS, we will then discuss various GALS design techniques proposed till date. We show the use of asynchronous FIFOs and asynchronous wrappers to realize GALS modules. Two wrapper design approaches are discussed: one being the asynchronous wrapper design proposed by Carlsson et al., in [4], and the other being the asynchronous wrapper design proposed in [1, 2]. An in-depth discussion and analysis of the wrapper design approach proposed in [1, 2] is provided based on the state transition graphs (STGs) that characterize the port-controller AFSMs. Various data transfer channel configurations that incorporate the wrapper port-controllers are designed and realized through VHDL codes, with their functioning verified through simulation results. Design examples showing the working of asynchronous wrappers to achieve point-to-point, synchronous-synchronous and synchronous-asynchronous data communication are provided. Finally, a design example to achieve multi-point data communication is realized. This example incorporates a previously proposed idea. We provide a modification to this idea by designing an arbiter that arbitrates between two separate requests coming into a multi-input port. Through the above design examples, the functionality and working of GALS asynchronous wrappers are verified, and recommendations for modifications are made to achieve flexible multi-point data communication.


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Graduation Date





Yuan, Jiann-Shiun


Master of Science in Electrical Engineering (M.S.E.E.)


College of Engineering and Computer Science


Electrical and Computer Engineering

Degree Program

Electrical Engineering








Release Date

December 2004

Length of Campus-only Access


Access Status

Masters Thesis (Open Access)