JFET, junction field, modeling, SPICE, capacitance, transistor
A compact model for four-terminal (independent top and bottom gates) junction field-effect transistor (JFET) is presented in this dissertation. The model describes the steady-state characteristics with a unified equation for all bias conditions that provides a high degree of accuracy and continuity of conductance, which are important for predictive analog circuit simulations. It also includes capacitance and leakage equations. A special capacitance drop-off phenomenon at the pinch-off region is studies and modeled. The operations of the junction fieldeffect transistor (JFET) with an oxide top-gate and full oxide isolation are analyzed, and a semi-physical compact model is developed. The effects of the different modes associated with the oxide top-gate on the JFET steady-state characteristics of the transistor are discussed, and a single expression applicable for the description of the JFET dc characteristics for all operation modes is derived. The model has been implemented in Verilog-A and simulated in Cadence framework for comparison to experimental data measured at Texas Instruments.
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Liou, Juin J.
Doctor of Philosophy (Ph.D.)
College of Engineering and Computer Science
Electrical Engineering and Computer Science
Length of Campus-only Access
Doctoral Dissertation (Open Access)
Ding, Hao, "Four Terminal Junction Field-effect Transistor Model For Computer-aided Design" (2007). Electronic Theses and Dissertations. 3145.