Cu, Classical Size Effect, Agglomeration, Alteration of resistivity, Thin film Stability, Au, Ru, Pt, Encapsulation


With continued shrinking of CMOS technology to reduce the gate delay times, an increase in the resistivity of the metal corresponding to the wire dimension is a concern. This phenomenon of increase in resistivity with decreasing dimension of the thin metallic film or interconnect is known as the "classical size effect". Various theories have been postulated to explain the phenomenon of classical size effect; these theories can be broadly classified as resistivity due to scattering arising from surface and grain boundaries. The total resistivity of metals depends on the electron scattering due to impurities, phonons, surfaces, grain boundaries, and other crystal defects. Managing the size effect in a practical and manufacturing way is of major concern to the microelectronics industry. Since each of the processes (phonon, surface and grain boundary scattering) adds to the resistivity and are interrelated, it further complicates managing the size effect. However, these effects have been separately studied. In this work, the effect of annealing on the classical size effect in Cu thin films deposited on SiO2 substrate is investigated. Polycrystalline Cu thin films having thicknesses in the range of 10nm to 200nm were ultra high vacuum sputter deposited on thermally grown SiO2 surfaces. The films were annealed at temperatures in the range of 150°C to 800°C in argon and argon+3% hydrogen gases. The un-annealed Cu thin films exhibit higher resistivity than the annealed films. The resistivities of un-annealed films were in good agreement with Mayadas and Shatzkes model. When annealed the films undergoes grain growth resulting in lowering the resistivities by about 20%-30% thereby confirming the role of grain size on resistivity of the film. However, there is a limit to annealing, i.e. agglomeration phenomenon. Agglomeration is a thermally activated process resulting in a reduction of the free energy of the film–substrate system and can occur well below the melting point of the material by surface and interfacial diffusion. The reduction of film-substrate interfacial energy, film-surface interfacial energy and stresses within the film are possible driving forces for agglomeration. This work also includes the study of agglomeration phenomenon. The agglomeration behavior of Cu is investigated and compared with that of Ru, Au and Pt thin films with thicknesses in the range of 10 nm to 100 nm UHV deposited on thermally grown SiO2 substrate. The films were annealed at temperatures in the range of 150°C to 800°C in argon and argon+3% hydrogen gases. Scanning electron microscopy was used to investigate the agglomeration behavior, and transmission electron microscopy was used to characterize the microstructure of the as-deposited and annealed films. The agglomeration sequence in all the films is found to follow a two step process of void nucleation and void growth. However, void growth in Au and Pt thin films is different from Cu and Ru thin films. Residual stress and adhesion were observed to play important part in deciding the mode of void growth in Au and Pt thin films. Lastly, it is also observed that the tendency for agglomeration can be reduced by encapsulating the metal film with an oxide overlayer, which in turn improves the resistivity of the thin film due to prolonged grain growth without film breakup.


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Graduation Date





Sundaram, Kalpathy


Master of Science in Electrical Engineering (M.S.E.E.)


College of Engineering and Computer Science


Electrical and Computer Engineering

Degree Program

Electrical Engineering








Release Date

May 2005

Length of Campus-only Access


Access Status

Masters Thesis (Open Access)