A new revolutionary concept was presented two decades ago, known as "semiconductor Superjunction (SJ) theory" to enhance the trade-off relationship between specific on resistance, Rsp, and off-state breakdown voltage, BV, in medium to high voltages (more than 100 V) power MOSFETs. The SJ concept was first applied and commercialized to vertical structures, but it hasn't been used yet in low voltage MOSFETs with lateral structures. This thesis provides a review of the most common structures, principles and design techniques for discrete power MOSFETs. It also presents a simulation study of the application of these SJ concepts in the design of a Low Voltage SJ LDMOS transistor, using TCAD software. To make the device commercially feasible, this device design targets aggressive goals such as an off-state Breakdown Voltage of 60V with Rsp of 20 miliohms per milimiter square. This study includes the analysis of the flow process for the fabrication of this transistor, using semiconductor technologies, and the simulation results, including Breakdown Voltage, on-state resistance, electric field distribution among others simulation analysis.
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Master of Science in Electrical Engineering (M.S.E.E.)
College of Engineering and Computer Science
Electrical Engineering and Computer Engineering
Length of Campus-only Access
Masters Thesis (Open Access)
Garcia, Jhonatan, "Three-Dimensional Simulation Study of Low Voltage (<100V) Superjunction Lateral DMOS power transistors" (2016). Electronic Theses and Dissertations. 5198.