The benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors are investigated in this thesis using Sentaurus TCAD simulation software. Optimizations to the SJ LDMOS were attempted such as adding a buffer layer to the device, but simulation and theoretical evidence point out that the benefits of the SJ technique are marginal at the 30 V application. A replacement for the SJ technique was sought, the floating P structure proved to be a good solution at the low voltage range due to its simpler cost effective process and performance gains achieved with optimization. A new idea of combining the floating P layer with shallow trench isolation is simulated yielding a low figure of merit (on state resistance x gate charge) of 5.93 mΩ-nC.
Master of Science in Electrical Engineering (M.S.E.E.)
College of Engineering and Computer Science
Electrical Engineering and Computer Engineering
Length of Campus-only Access
Masters Thesis (Campus-only Access)
Salih, Aiman, "LDMOS Power Transistor Design and Evaluation using 2D and 3D Device Simulation" (2017). Electronic Theses and Dissertations. 5750.