Low-Temperature Bicmos Gate Pull-Down Delay Analysis
Abbreviated Journal Title
Int. J. Electron.
BIPOLAR-TRANSISTORS; OPTIMIZATION; PERFORMANCE; OPERATION; SILICON; DEVICE; SPEED; Engineering, Electrical & Electronic
Temperature-dependent BiCMOS gate delay analysis including high current transient has been developed. The model accounts for the high electric field effect in the nMOS transistor and high current effects in the bipolar transistor for a wide temperature range. In examining the switching transient of a BiCMOS driver, the base pushout mechanism exhibits a detrimental effect on the gate propagation delay at room temperature, while the current gain degradation and temperature-dependent intrinsic density are responsible for increasing the BiCMOS gate pull-down delay at low temperature. The analytical equations provide evaluation of the sensitivity of process and device parameters to circuit performance at different temperatures. Computer simulation of a BiNMOS driver using the present analysis is compared with a PISCES simulation in support of the physical reasoning.
International Journal of Electronics
"Low-Temperature Bicmos Gate Pull-Down Delay Analysis" (1995). Faculty Bibliography 1990s. 1250.