Evaluation of RF electrostatic discharge (ESD) protection in 0.18-mu m CMOS technology
Abbreviated Journal Title
CIRCUITS; DESIGN; Engineering, Electrical & Electronic; Nanoscience & Nanotechnology; Physics, Applied
Electrostatic discharge (ESD) protection design is challenging for RF integrated circuits (ICs) because of the trade-off between the ESD robustness and parasitic capacitance. ESD protection devices are fabricated using the 0.18-mu m RF CMOS process and their RF ESD characteristics are investigated by the transmission line pulsing (TLP) tester. The results suggest that the silicon controlled rectifier (SCR) is superior to the diode and NMOS from the perspective of ESD robustness and parasitic, but the SCR nevertheless possesses a longer turn-on time. (C) 2008 Elsevier Ltd. All rights reserved.
"Evaluation of RF electrostatic discharge (ESD) protection in 0.18-mu m CMOS technology" (2008). Faculty Bibliography 2000s. 290.