SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests
Abbreviated Journal Title
IEEE J. Solid-State Circuit
analog circuits; BSIM3v3 model; statistical circuit simulation; transistor mismatch; TRANSISTORS; Engineering, Electrical & Electronic
This paper reports a MOS transistor mismatch model applicable for submicron CMOS technologies and developed based on the industry standard BSIM3v3 model. A simple and unified expression was derived to formulate the effect of MOSFET mismatch on drain current variance. A way to quickly estimate the drain current mismatch was also suggested. The model has been integrated into HSPICE, and results obtained from simulation and measurements were compared.
Ieee Journal of Solid-State Circuits
"SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests" (2001). Faculty Bibliography 2000s. 3021.