Statistical modeling of MOS devices for parametric yield prediction
Abbreviated Journal Title
INTEGRATED-CIRCUITS; TRANSISTORS; METHODOLOGY; MISMATCH; Engineering, Electrical & Electronic; Nanoscience & Nanotechnology; Physics, Applied
In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing, In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread (i.e., parametric yield) of MOS devices and circuits due to the process variations. To illustrate their applications, the models are applied to the 0.25 mum CMOS technology, and measured data are included in support of the model calculations. (C) 2002 Elsevier Science Ltd. All rights reserved.
"Statistical modeling of MOS devices for parametric yield prediction" (2002). Faculty Bibliography 2000s. 3324.