Multiterminal net routing for partial crossbar-based multi-FPGA systems
Abbreviated Journal Title
IEEE Trans. Very Large Scale Integr.
branch-and-price; field-programmable gate arrays (FPGAs) architecture; FPGA routing; integer programming; interconnect optimization; layout; synthesis; LOGIC EMULATION; Computer Science, Hardware & Architecture; Engineering, Electrical &; Electronic
Multi-FPGA (field-programmable gate arrays) systems are used as custom computing machines to solve compute-intensive problems and also in the verification and prototyping of large circuits. In this paper, we address the problem of routing multiterminal nets in a multi-FPGA system that uses partial crossbars as interconnect structures. First, we model the multiterminal routing problem as a partitioned bin-packing problem and formulate it as an integer linear programming problem where the number of variables is exponential. A fast heuristic is applied to compute an upper bound on the routing solution. Then, a column generation technique is used to solve the linear relaxation of the initial master problem in order to obtain a lower bound on the routing solution. This is followed by an iterative branch-and-price procedure that attempts to find a routing solution somewhere between the two established bounds. In this regard, the proposed algorithm guarantees an exact-routing solution by searching a branch-and-price tree. Due to the tightness of the bounds, the branch-and-price tree is small resulting in shorter execution times. Experimental results are provided for different netlists and board configurations in order to demonstrate the algorithms performance. The obtained results show that the algorithm finds an exact routing solution in a very short time.
Ieee Transactions on Very Large Scale Integration (Vlsi) Systems
"Multiterminal net routing for partial crossbar-based multi-FPGA systems" (2003). Faculty Bibliography 2000s. 3730.