Energy-efficient self-timed circuit design using supply voltage scaling
Abbreviated Journal Title
IEE Proc.-Circuit Device Syst.
LOW-POWER; OPTIMIZATION; Engineering, Electrical & Electronic
Energy-efficient design for self-timed circuits is investigated. Null convention logic is employed to construct speed-independent self-timed circuits. For error-free computation, the supply voltage automatically tracks the input data rate so that the supply voltage can be kept as small as possible while maintaining the speed requirement. For error-tolerable computation, such as soft digital signal processing, further energy saving is achieved at the cost of signal-to-noise ratio when an ultralow supply voltage is applied. Cadence simulation shows that 40 to 70% power can be saved by introducing -15 to -11 dB error in typical speech signal processing.
Iee Proceedings-Circuits Devices and Systems
"Energy-efficient self-timed circuit design using supply voltage scaling" (2004). Faculty Bibliography 2000s. 4508.