Substrate current, gate current and lifetime prediction of deep-submicron nMOS devices
Abbreviated Journal Title
MOS devices; reliability; lifetime model; substrate current; gate; current; HOT-CARRIER DEGRADATION; INTERFACE STATES; CHANNEL MOSFETS; OXIDE; INTERFACE; N-CHANNEL; SILICON; MODEL; BREAKDOWN; MONITOR; FILMS; Engineering, Electrical & Electronic; Physics, Applied; Physics, ; Condensed Matter
Experimental results are presented to indicate that the widely used power-law models for lifetime estimation are questionable for deep-submicron (<0.25 mun) MOS devices, particularly for the case of large substrate current stressing. This observation is attributed to the presence of current components, such as the gate tunneling current and base current of parasitic bipolar transistor, that do not induce device degradation. A more effective extrapolation method is proposed as an alternative for the reliability characterization of deep-submicron MOS devices. (C) 2004 Elsevier Ltd. All rights reserved.
"Substrate current, gate current and lifetime prediction of deep-submicron nMOS devices" (2005). Faculty Bibliography 2000s. 5102.