Title

Substrate current, gate current and lifetime prediction of deep-submicron nMOS devices

Authors

Authors

Z. Cui; J. J. Liou; Y. Yue;H. Wong

Comments

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Abbreviated Journal Title

Solid-State Electron.

Keywords

MOS devices; reliability; lifetime model; substrate current; gate; current; HOT-CARRIER DEGRADATION; INTERFACE STATES; CHANNEL MOSFETS; OXIDE; INTERFACE; N-CHANNEL; SILICON; MODEL; BREAKDOWN; MONITOR; FILMS; Engineering, Electrical & Electronic; Physics, Applied; Physics, ; Condensed Matter

Abstract

Experimental results are presented to indicate that the widely used power-law models for lifetime estimation are questionable for deep-submicron (<0.25 mun) MOS devices, particularly for the case of large substrate current stressing. This observation is attributed to the presence of current components, such as the gate tunneling current and base current of parasitic bipolar transistor, that do not induce device degradation. A more effective extrapolation method is proposed as an alternative for the reliability characterization of deep-submicron MOS devices. (C) 2004 Elsevier Ltd. All rights reserved.

Journal Title

Solid-State Electronics

Volume

49

Issue/Number

3

Publication Date

1-1-2005

Document Type

Article

Language

English

First Page

505

Last Page

511

WOS Identifier

WOS:000226942300032

ISSN

0038-1101

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