Scheduling setup changes at bottleneck workstations in semiconductor manufacturing
Abbreviated Journal Title
Prod. Plan. Control
dispatching rules; re-entrant flow; WAFER FABRICATION; Engineering, Industrial; Engineering, Manufacturing; Operations Research; & Management Science
This paper presents a scheduling heuristic to aid the operators in semiconductor fabrication facilities ( commonly referred to as fabs) in choosing what type of lots to process next and whether to change machine setup in order to reduce cycle time. Specifically, this study focused on developing a scheduling heuristic for ion implanters at Cirent Semiconductor ( currently Agere Systems) in Orlando, Florida, where implanters are considered to be a bottleneck workstation. The re-entrant flow of production passes several times through the implanters at different stages of the wafer production, requiring changes to the current settings of the workstations and thus incurring a significant setup time. The scheduling heuristic aims at balancing workload levels for implanters processing jobs at different stages of the wafer production lifecycle. This is accomplished by first processing those jobs that contribute most to the increase in inventory levels at the bottleneck workstation. The measures used to evaluate the performance of the proposed heuristic were mean cycle time, mean work in process (WIP), and standard deviation of cycle time. The performance of the proposed heuristic was compared with the scheduling rules currently in use and other commonly used dispatching rules using a validated simulation model. Simulation results showed that the introduced heuristic performs better than all other rules in terms of mean cycle time and WIP in all cases, and better in terms of standard deviation of cycle time for most cases tested. The heuristic can be used at any bottleneck workstation that processes products at different stages of their production cycle and that requires a significant setup time.
Production Planning & Control
"Scheduling setup changes at bottleneck workstations in semiconductor manufacturing" (2006). Faculty Bibliography 2000s. 6096.