Modelling and simulation of off-chip communication architectures for high-speed packet processors
Abbreviated Journal Title
J. Syst. Softw.
network processors; memory management; linecards; interconnect systems; k-Ary n-cube networks; shared-bus; PERFORMANCE; Computer Science, Software Engineering; Computer Science, Theory &; Methods
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications architectures for line cards. The simulator uses the state-of-the-art software design techniques to provide the user with a flexible, robust and comprehensive tool that can evaluate k-ary n-cube based network topologies under non-uniform traffic patterns. The simulator provides full control over essential network parameters and flow control mechanisms such as virtual channels and sub-channeling. We compare three low-dimensional k-ary n-cube based interconnects that can fit into the physical limitations on line cards, where each one of these interconnects has multiple processor-memory configurations. Performance results show that k-ary n-cube architectures perform better than existing interconnects, and they can sustain current line rates and higher. In addition, we provide performance tradeoffs between multiple flow control mechanisms and performance metrics such as throughput, routing accuracy, failure rate and interconnect utilization. (C) 2006 Elsevier Inc. All rights reserved.
Journal of Systems and Software
"Modelling and simulation of off-chip communication architectures for high-speed packet processors" (2006). Faculty Bibliography 2000s. 6117.