A high throughput 3D-bus interconnect for network processors
Abbreviated Journal Title
network processors; memory management; line cards; interconnect systems; k-ary n-cube networks; Computer Science, Hardware & Architecture; Computer Science, Theory &; Methods; Engineering, Electrical & Electronic
Deep layer processing and increasing line rates present a memory challenge to processor-memory communications located on network line cards. In this paper, we introduce a packet-based, off-chip interconnect to increase the throughput of memory system currently used on line cards. The 3D-bus architecture allows multiple packet processing elements on a line card to access multiple memory modules. Our network-on-board includes a routing protocol as well as a node switching mechanism to minimize packet congestion and packet loss. The main advantage of the proposed architecture is to increase the network processor off-chip memory bandwidth while diminishing the latency otherwise caused by the single bus competition. Performance results show that our interconnect significantly outperforms its competitors, such as shared-bus, PCI Express, infiniband and HyperTransport, reaching peak throughput beyond 400 Gbps. Moreover, it provides other high performance qualities including low latency, off-chip scalability, low transmission failure-rate and high memory bandwidth. (c) 2005 Elsevier B.V. All rights reserved.
Microprocessors and Microsystems
"A high throughput 3D-bus interconnect for network processors" (2006). Faculty Bibliography 2000s. 6307.