Dynamic voltage stress effects on nMOS varactor
Abbreviated Journal Title
Engineering, Electrical & Electronic; Nanoscience & Nanotechnology; Physics, Applied
The degradations in the nMOS device due to high-frequency (900 MHz) dynamic stress are shown experimentally. The stress-induced shifts in DC and larger-signal C-V characteristics are presented. Although the high-frequency stress-induced degradations are much smaller than DC stress, the effects on C-V curves and quality factor cannot be neglected. An nMOS LC oscillator, wherein the varactor is operated under the same dynamic bias conditions as in the stress experiment, has been evaluated through Cadence Spectre simulation. The performance of the LC oscillator degrades significantly due to the dynamic stress.
Article; Proceedings Paper
"Dynamic voltage stress effects on nMOS varactor" (2006). Faculty Bibliography 2000s. 6747.