Self-timed architecture for masked successive approximation analog-to-digital conversion
Abbreviated Journal Title
J. Circuits Syst. Comput.
asynchronous digital systems; self-timed designs; analog-to-digital; conversion; null convention logic; successive approximation; CIRCUITS; Computer Science, Hardware & Architecture; Engineering, Electrical &; Electronic
In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-mu m CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.
Journal of Circuits Systems and Computers
"Self-timed architecture for masked successive approximation analog-to-digital conversion" (2007). Faculty Bibliography 2000s. 7313.