A general approach for high yield fabrication of CMOS-compatible all-semiconducting carbon nanotube field effect transistors
Abbreviated Journal Title
ELECTRONIC-STRUCTURE; SINGLE; DIELECTROPHORESIS; DIAMETER; DENSITY; ARRAYS; PERFORMANCE; DISPERSION; MOBILITY; DEVICES; Nanoscience & Nanotechnology; Materials Science, Multidisciplinary; Physics, Applied
We report strategies to achieve both high assembly yield of carbon nanotubes at selected positions of the circuit via dielectrophoresis (DEP) and field effect transistor (FET) yield using an aqueous solution of semiconducting-enriched single-walled carbon nanotubes (s-SWNTs). When the DEP parameters were optimized for the assembly of individual s-SWNTs, 97% of the devices showed FET behavior with a maximum mobility of 210 cm(2) V-1 s(-1), on-off current ratio similar to 10(6) and on-conductance up to 3 mu S, but with an assembly yield of only 33%. As the DEP parameters were optimized so that one to five s-SWNTs are connected per electrode pair, the assembly yield was almost 90%, with similar to 90% of these assembled devices demonstrating FET behavior. Further optimization gave an assembly yield of 100% with up to 10 SWNTs per site, but with a reduced FET yield of 59%. Improved FET performance including higher current on-off ratio and high switching speed were obtained by integrating a local Al2O3 gate to the device. Our 90% FET with 90% assembly yield is the highest reported so far for carbon nanotube devices. Our study provides a pathway which could become a general approach for the high yield fabrication of complementary metal oxide semiconductor (CMOS)-compatible carbon nanotube FETs.
"A general approach for high yield fabrication of CMOS-compatible all-semiconducting carbon nanotube field effect transistors" (2012). Faculty Bibliography 2010s. 2786.