Abstract

The graphics generator hardware is an important component of flight-training simulators. The function of this hardware is to generate 3D perspective images at rates of 30 frames per second to produce realistic out-ofwindow scenes viewed by the crew under training. Within most graphics generator hardware are array processors which achieve high computation throughput necessary to generate real-time processing. The function of the array processors is to transform, clip, rotate and perspective project the data base into screen coordinates for use by the graphic generator. A FIMD (few instructions multiple data) systolic architecture is proposed to achieve high computational throughput that is required of the array processor. The proposed systolic architecture will implement graphic transformations. A software simulation of the proposed architecture was done to resemble the operations, functions, and communication protocols of a graphic array processor in a Computer Image Generation System. Finally, a comparison was done with the FIMD systolic architecture implementation and another existing graphic processor in terms of speed, versatility, and cost.

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Graduation Date

1988

Semester

Summer

Advisor

Papadourakis, George M.

Degree

Master of Science (M.S.)

College

College of Engineering

Department

Computer Engineering

Format

PDF

Pages

112 p.

Language

English

Rights

Public Domain

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Identifier

DP0025755

Subjects

Dissertations, Academic -- Engineering; Engineering -- Dissertations, Academic

Accessibility Status

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