Keywords

Algorithms, Division, Pipelines

Abstract

A realization of a division algorithm suitable for high speed pipeline and realtime processors is presented. Implementation of the divide algorithm can be achieved by utilizing LSI / VLSI gate array technology. The divider performs precision, high speed 9 bit sign magnitude division. The design consist of combinational logic, where input and output data are latched into input and output registers. Data propagates through 16 divide stages. The n'th stage generates the n'th quotient bit upon receiving the updated dividend and controls from the previous stage. A simulation program is developed to verify the algorithm, and an analysis for speed performance and cost is provided. Other division algorithms are discussed.

Notes

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Graduation Date

1984

Semester

Spring

Advisor

Petrasko, Brian E.

Degree

Master of Science (M.S.)

College

College of Engineering

Degree Program

Engineering

Format

PDF

Pages

39 p.

Language

English

Rights

Public Domain

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Identifier

DP0015592

Included in

Engineering Commons

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