Keywords

Frequency dividers, Frequency synthesizers, Phase locked loops

Abstract

This thesis describes the design, implementation and testing of a UHF frequency synthesizer. The synthesizer is designed to provide a sine wave output programmable from 400 MHz to 500 MHz in 0.1 MHz increments. The synthesis technique utilized is Digital Coherent Indirect Synthesis. This technique uses phase locking to provide a range of stable output frequencies all derived from a single crystal reference. Component design and system level analysis are presented in detail.

Notes

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Graduation Date

1985

Semester

Fall

Advisor

Belkerdid, Madjid A.

Degree

Master of Science (M.S.)

College

College of Engineering

Degree Program

Engineering

Format

PDF

Language

English

Rights

Public Domain

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Identifier

DP0018311

Included in

Engineering Commons

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