Keywords

Microcomputers, Microprocessors

Abstract

This thesis examines the performance of the Intel 8089 integrated I/0 processor through a predictive performance model for the I/0 subsystem architectures available to the designer of an iAPX 86 system. The model provides system throughput estimates and is intended to be used prior to any detailed design. The derivation of the model is followed by a description of a prototype system which is used to provide actual throughput measurements. These measurements are compared with the model predictions to evaluate the model error and its utility. The model estimates are then combined with subsystem cost data to gauge the cost-effectiveness of the 8089.

Graduation Date

1983

Advisor

Towle, H.C.

Degree

Master of Science (M.S.)

College

College of Engineering

Degree Program

Engineering

Format

PDF

Pages

149 p.

Language

English

Rights

Public Domain

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Identifier

DP0014069

Included in

Engineering Commons

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