Copper (Cu) through-silicon via (TSV) is an essential structural and functional element in three-dimensional integration circuits (3D ICs), which offers substantial improvements in integration density, form factor, device performance, and power efficiency. However, Cu-filled TSVs are exposed to multiple thermal cycles during fabrication, test and operation, which lead to the development of considerable thermal stresses, in and around the vias, due to the large mismatch of the coefficient of thermal expansion (CTE) between Cu and silicon (Si). The stress subsequently raises reliability concerns, among which, via extrusion is an important one. Via extrusion can damage the adjacent components, in particular the back-end-of-line (BEOL) interconnect layers, to degrade the 3D IC structure and result in the device failure. More recently, it has been revealed that for a large population of TSVs, there is a wide spread in the values of via extrusion. Although a few approaches such as post-plating annealing and via dimension scaling have been used to reduce the average values of via extrusion, these methods are not effective in controlling the statistical spread of via extrusion. Controlling via extrusion, especially its statistical spread, remains an important issue, as the reliability of a 3D IC containing many TSVs will be determined by the weakest link, i.e., the 0.1% of TSVs with the highest extrusion heights. This work proposes the application of a metallic cap layer as a novel and promising solution to TSV extrusion variation and investigates its effects on TSV extrusion behavior and the underlying mechanisms with the ultimate goal of assessing and addressing this reliability risk for 3D integration technology. The mechanisms of extrusion and their correlation to the extrusion morphology and the Cu microstructural characteristics are examined in order to trace the root cause(s) of the high statistical spread in TSV extrusion and the effect of cap layer in controlling the extrusion variation. Experimental results first establish the application of different metallic cap layers on TSV samples and demonstrate that Tantalum (Ta) is an effective cap material to control the magnitude of extrusion, and more importantly, its range. Further cap/via interface characterizations reveals that Ta offers a dense and continuous interface with Cu via which is indeed beneficial in suppressing the mass transport at the via surface. The curvature behavior of Cu TSV structures, with and without the presence of Ta cap layer, are also investigated using the substrate curvature method. The substrate curvature measurement is employed to investigate the effect of Ta cap layer on the Cu TSV stress state. The effect of pitch size on via extrusion and its statistical variation is studied in combination with the cap layer implementation, to further investigate the effect of stress on extrusion mechanisms. Smaller pitch distance is shown to surge the extrusion magnitude but with insignificant effect on extrusion spread. Additionally, the effect of pitch distance on extrusion morphology is investigated. The contribution of dislocation creep mechanism influenced by the pitch-dependent stress is also discussed by statistical analysis of various extrusion morphologies. The effect of cap layer on microstructure is studied to establish a more clear understanding of the microstructure-dependent mechanisms of extrusion. The microstructure-extrusion correlation of vias with different extrusion behaviors, including extrusion height and morphology, are studied and the effect of grain size, grain boundary type and grain boundary misorientation angle on the extrusion behavior is investigated. The contribution of grain boundary diffusion creep and grain sliding mechanisms on via extrusion is further discussed by investigating the formation of voids in the uncapped and capped vias.
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Doctor of Philosophy (Ph.D.)
College of Engineering and Computer Science
Materials Science and Engineering
Materials Science and Engineering
Length of Campus-only Access
Doctoral Dissertation (Campus-only Access)
Jalilvand, Golareh, "Investigation of Via Extrusion and The Effect of Cap Layer for 3D Integrated Circuits" (2020). Electronic Theses and Dissertations, 2020-. 611.