ORCID

0000-0002-5819-1773

Keywords

PPA Optimizations, Compiler, Register-Transfer Level, AI for EDA, Microarchitecture, ASIC

Abstract

The exponential growth in computational demands has outpaced traditional Moore's Law scaling, necessitating innovations in hardware design methodologies. Traditional hardware design flows defer critical power, performance, and area (PPA) optimizations to late stages such as Logic Synthesis and Physical Design, creating prolonged feedback cycles that limit performance scaling. As designs grow in complexity, these late-stage optimization bottlenecks worsen, making it increasingly difficult to meet the desired PPA constraints for modern SoC designs with billions of transistors.

To address this limitation, this dissertation introduces the concept of left-shifting the hardware design process by enabling PPA optimizations at the earlier RTL stage. First, this dissertation presents CircuitSeer, a deep learning framework that accurately predicts post-place and route (PnR) delay metrics directly from pre-synthesis designs, eliminating the need for time-consuming Logic Synthesis and Physical Design. This framework provides orders of magnitude faster delay feedback to digital designers compared to traditional Logic Synthesis and Physical Design flows, enabling timing optimizations during the RTL phase. Next, it extends this endeavor by introducing CircuitRetimer, a novel compiler-driven framework for register transfer level (RTL) sequential optimization. Unlike traditional approaches that perform retiming after logic synthesis, CircuitRetimer operates directly on RTL, enabling early-stage register repositioning while preserving design semantics and readability. This work demonstrates CircuitRetimer's application in enabling microarchitectural design space exploration of PPA-optimized pipelined architectures from early-stage combinational RTL, facilitating the area, delay tradeoff exploration necessary to improve PPA.

Completion Date

2025

Semester

Spring

Committee Chair

Lin, Mingjie

Degree

Doctor of Philosophy (Ph.D.)

College

College of Engineering and Computer Science

Department

Department of Electrical and Computer Engineering

Identifier

DP0029306

Document Type

Dissertation/Thesis

Campus Location

Orlando (Main) Campus

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