High-Speed Parallel Vlsi Architectures For Image Decorrelation
Abbreviated Journal Title
Int. J. Pattern Recognit. Artif. Intll.
CODEC; COMPRESSION; DECOMPRESSION; DECORRELATION; JPEG; PARALLEL; ARCHITECTURE; PREDICTIVE CODING; VLSI; COMPRESSION; Computer Science, Artificial Intelligence
We present a new high speed parallel architecture and its VLSI implementation to design a special purpose hardware for real-time lossless image compression/decompression using a decorrelation scheme. The proposed architecture can easily be implemented using state-of-the-art VLSI technology. The hardware yields a high compression rate. A prototype 1-micron VLSI chip based on this architectural idea has been designed. The scheme is favourably comparable to the lossless JPEG standard image compression schemes. We also discuss the parallelization issues of the lossless JPEG standard still compression schemes and their difficulties.
International Journal of Pattern Recognition and Artificial Intelligence
"High-Speed Parallel Vlsi Architectures For Image Decorrelation" (1995). Faculty Bibliography 1990s. 1260.