Array Noise-Analysis For Multimegabit Dram Design
Abbreviated Journal Title
Int. J. Electron.
Engineering, Electrical & Electronic
An analytical model for bit-line coupling noise in various DRAM architectures has been developed. The analytical expressions developed provide insight into the charge redistribution when the word lines turn on. They are also useful for determining the noise-to-signal ratio and for designing the sense amplifier circuit. Noise extracted from SPICE circuit simulation is included and is compared against the results from the present analytical model. Good agreement is found.
International Journal of Electronics
"Array Noise-Analysis For Multimegabit Dram Design" (1993). Faculty Bibliography 1990s. 966.