Impact of SOI Thickness on FUSI-Gate CESL CMOS Performance and Reliability
Abbreviated Journal Title
IEEE Trans. Device Mater. Reliab.
Compressive strain; contact etch stop layer (CESL); fully silicided; (FUSI); gate oxide breakdown; hot electron; low-noise amplifier (LNA); negative bias temperature instability (NBTI); oxide trap charge; power; amplifier; reliability; silicon on insulator (SOI); tensile strain; HOT-CARRIER RELIABILITY; P-MOSFETS; STRESS; DEGRADATION; OXIDE; BIAS; TECHNOLOGIES; GENERATION; DEPENDENCE; INTERFACE; Engineering, Electrical & Electronic; Physics, Applied
The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided (FUSI)-metal-gate silicon-on-insulator (SOI) MOSFETs is investigated. High strain from a contact etch stop layer (CESL) in FUSI-gate transistors increases channel mobility and drain current driving. A CESL nMOSFET with a thick SOI demonstrates increased hot-electron degradation than its thin SOI counterpart. However, a ring oscillator using thick SOI transistors shows less gate delay due to enhanced drain current. Strained p-channel transistors with a large SOI thickness are more vulnerable to negative bias temperature instability. The oxide trap charge also plays an important role in the circuit performance degradation of RF low-noise and power amplifiers.
Ieee Transactions on Device and Materials Reliability
"Impact of SOI Thickness on FUSI-Gate CESL CMOS Performance and Reliability" (2011). Faculty Bibliography 2010s. 1169.