vfTLP-V-TH: A new method for quantifying the effectiveness of ESD protection for the CDM classification test
Abbreviated Journal Title
MOSFET DEGRADATION; OXIDE; Engineering, Electrical & Electronic; Nanoscience & Nanotechnology; Physics, Applied
A new methodology for quantifying the effectiveness of CDM protection circuits and CDM robustness of I/O circuits is presented in this paper. This method, referred to as the vfTLP-V-TH, consists of applying vfTLP stresses to test structures composed of the ESD protection and the device or circuit to be protected: a MOS device or a MOS inverter. The protected structures are used as monitors and shifts in their characteristics, such as MOS threshold voltage V-TH and saturation current I-DD, are used to probe device failure criteria. (C) 2012 Elsevier Ltd. All rights reserved.
"vfTLP-V-TH: A new method for quantifying the effectiveness of ESD protection for the CDM classification test" (2013). Faculty Bibliography 2010s. 4947.