Compact failure modeling for devices subject to electrostatic discharge stresses - A review pertinent to CMOS reliability simulation
Abbreviated Journal Title
Electrostatic discharge (ESD); Gate oxide breakdown; Junction thermal; failure; Thermal network; Transmission line pulsing (TLP); Transient; power law (TPL); GATE OXIDE BREAKDOWN; SEMICONDUCTOR-DEVICES; SILICON DIOXIDE; ESD; TRANSISTORS; STATISTICS; PROTECTION; PULSE; Engineering, Electrical & Electronic; Nanoscience & Nanotechnology; Physics, Applied
This paper reviews the physical mechanisms and compact modeling approaches of two physical damages in MOS devices induced by electrostatic discharge (ESD) stresses; namely gate oxide breakdown and thermal failures. Theories underlying the failure mechanism are discussed and compact models that can be used to monitor ESD induced gate oxide breakdown and thermal failure are developed. Related work reported in the literature is discussed, and benchmarking of measurement data versus simulation results are included in support of the modeling work. (C) 2014 Elsevier Ltd. All rights reserved.
"Compact failure modeling for devices subject to electrostatic discharge stresses - A review pertinent to CMOS reliability simulation" (2015). Faculty Bibliography 2010s. 6704.