An Adaptive Supply-Voltage Scheme For Low Power Self-Timed Cmos Digital Design
Capacitance; Circuit simulation; Clocks; Communication system control; Delay; Dynamic voltage scaling; Logic circuits; Power dissipation; Signal detection; Timing
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data rate of the data path so that the supply-voltage can be kept as small as possible while maintaining the speed requirement. This adaptive supply-voltage scheme employs the handshake signals directly to detect the speed of data path without using FIFO buffer. This leads to a very simple logic control whose power loss is negligible. Cadence SPICE simulation shows the effectiveness of this scheme for low power applications based on 0.18 μm CMOS process.
Proceedings of the IEEE International Conference on VLSI Design
Number of Pages
Article; Proceedings Paper
Source API URL
Kuang, W. and Yuan, J. S., "An Adaptive Supply-Voltage Scheme For Low Power Self-Timed Cmos Digital Design" (2003). Scopus Export 2000s. 1977.