Title

Optimization Of On-Chip Esd Protection Structures For Rf Operations

Keywords

Breakdown voltage; Circuits; Clamps; Diodes; Electrostatic discharge; Humans; Parasitic capacitance; Protection; Radio frequency; Variable structure systems

Abstract

Diodes are key components in on-chip electrostatic discharge (ESD) protection design. As the operating frequency of the microchip being protected against the ESD continues to increase, the parasitic capacitance associated with the diodes in the ESD structure starts to impose problems for RF operation. This paper presents a systematic approach to optimize the diode structure for minimal parasitic capacitance based on the requirements of breakdown voltage and heat dissipation. The device simulator Atlas, with mix-mode simulation capability, is calibrated against measurement data and used to carry out the optimization. An optimized diode structure with a parasitic capacitance of less than 30 fF at an operating frequency of 10 GHz and ESD charging voltage of 1 kV has been suggested.

Publication Date

1-1-2002

Publication Title

IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications

Volume

2002-January

Number of Pages

36-43

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/EDMO.2002.1174927

Socpus ID

84949294713 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84949294713

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