Modelling And Simulation Of Off-Chip Communication Architectures For High-Speed Packet Processors


K-ary n-cube networks; Line-card design; Network processor; Off-chip inter-connects; Simulation framework; Worm-hole routing


In this work, we propose an event-driven, custom-designed interconnect simulation environment to evaluate the performance of packet-based off-chip k-ary n-cube interconnect architectures for line cards. The simulator uses the state-of-the-art software design techniques to provide the user with a flexible yet robust tool, that can emulate multiple interconnect architectures under non-uniform traffic patterns. Moreover, the simulator offers the user with full control over network parameters, performance enhancing features and simulation time frames that make the platform as identical as possible to the real line card physical and functional properties. The k-ary n-cube architectures allow multiple packet processing elements on a line card to access multiple memory modules. In addition, they can sustain current line rates and higher, while distributing the load among multiple memories. The objective of the proposed simulator is to compare among different off-chip interconnect architectures for network line cards and determine which interconnect can significantly increase the memory bandwidth and the overall system throughput.

Publication Date


Publication Title

Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005

Number of Pages


Document Type

Article; Proceedings Paper

Personal Identifier


Socpus ID

33344465500 (Scopus)

Source API URL


This document is currently not available here.