High performance architectures for chip-to-chip communications on network line cards
Abbreviated Journal Title
J. High Speed Netw.
network processors; memory management; linecards; interconnect systems; k-ary n-cube networks; shared-bus; Computer Science, Hardware & Architecture; Computer Science, Information; Systems; Engineering, Electrical & Electronic; Telecommunications
In this paper, we propose two hypercube-based, off-chip interconnect architectures, called 3D-interconnects, to communicate between processing elements and memory modules located on network linecards. Our main goal is to increase the throughput of the memory system since most currently deployed linecard designs reach their maximum transfer rate. Moreover, line rates are constantly increasing while at the same time more data and functionality are embedded in each packet. The 3D-interconnect architectures allow multiple packet processing elements on a linecard to access multiple memory modules. The novelty of the proposed interconnects is their application and implementation as off-chip interconnects on the linecard board. Our interconnects include multiple, highly efficient techniques to route, switch, and control packet flows in order to minimize congestion spots within the interconnects and packet loss. Performance results show that both 3D-interconnects, studied in this paper, achieve high throughput, low latency results surpassing other common interconnects currently deployed. Furthermore, the interconnects were able to sustain high traffic load while keeping low failure rates and high bandwidth utilization levels.
Journal of High Speed Networks
"High performance architectures for chip-to-chip communications on network line cards" (2007). Faculty Bibliography 2000s. 7104.