Reference voltage generation scheme enhancing speed and reliability for 1T1C-type FRAM
Abbreviated Journal Title
CMOS analogue integrated circuits; differential amplifiers; field effect; transistors; low noise amplifiers; IIP3 common-gate LNA; post-linearisation technique; low noise amplifier; cross-coupled; post-distortion technique; PMOS; auxiliary FET; third-order nonlinear; currents cancellation; CMOS technology; differential low noise; amplifier; power 6; 8 mW; size 0; 18 mum; noise figure 3; 4 dB; voltage; 1; 8 V; Engineering, Electrical & Electronic
An improved reference voltage generation scheme is proposed for a 1T1C-type ferroelectric random access memory (FRAM), in which the circuit referring to reference cells is redefined and the data are written into reference cells at random between '1' and '0' depending on the voltages of the bitlines during every operation cycle. Compared with conventional schemes, it can not only realise higher access speed for memory, but also can enhance its reliability by resolving the imprint and relieving the fatigue relating to ferroelectric capacitors in the device. Functional verification for the experimental prototype utilising the proposed scheme has been implemented.
"Reference voltage generation scheme enhancing speed and reliability for 1T1C-type FRAM" (2014). Faculty Bibliography 2010s. 5514.