In recent years, innovations in machine learning using artificial neural networks (ANN) have significantly increased and led to various applications like image recognition, text classification, machine translation, sequence recognition, etc. Earlier, research was focused on software-based DBNs, which are implemented on conventional von-Neumann architectures that provided flexibility but had few limitations. Recent studies have implemented hardware-based designs like FPGA-based, CMOS based, RRAM-based, and MRAM-based designs to overcome these limitations. Hybrid CMOS-MTJ-based RBMs provided significant area and energy improvements compared to other techniques. We herein implemented Spatial and Temporal redundant probabilistic interpolation network to improve the accuracy and provide fault tolerance with the help of a low-power and area-efficient novel SHE-MTJ-based majority gate. Also, Progressive Modular Redundant Network is Proposed to enhance reduced footprint when compared with the Spatial modular Redundant network. Results show that the SHE-MTJ-based majority gate provides 32.1% area reduction and 54.5% energy reduction compared to the conventional CMOS-based design. Also, the simulation results show that the proposed model improved 36% in Error rate, in addition to latency improvements when compared with baseline models. An accuracy comparison of all the redundant models for two different topologies, 784x200x10, and 784x200x200x10, and for different activation functions including Sigmoid, Square root and Square indicate viability of the methods developed with respect to area and energy metrics.
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Master of Science in Electrical Engineering (M.S.E.E.)
College of Engineering and Computer Science
Electrical and Computer Engineering
Length of Campus-only Access
Masters Thesis (Open Access)
Thummala, Harshavardhan Reddy, "Reduced Footprint Probabilistic Inference Networks Using Novel Hybrid SHE-MTJ/CMOS Based Majority Gate" (2022). Electronic Theses and Dissertations, 2020-. 1446.