Low-Temperature Bicmos Gate Pull-Down Delay Analysis

    Authors

    J. S. Yuan

    Comments

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    Abbreviated Journal Title

    Int. J. Electron.

    Keywords

    BIPOLAR-TRANSISTORS; OPTIMIZATION; PERFORMANCE; OPERATION; SILICON; DEVICE; SPEED; Engineering, Electrical & Electronic

    Abstract

    Temperature-dependent BiCMOS gate delay analysis including high current transient has been developed. The model accounts for the high electric field effect in the nMOS transistor and high current effects in the bipolar transistor for a wide temperature range. In examining the switching transient of a BiCMOS driver, the base pushout mechanism exhibits a detrimental effect on the gate propagation delay at room temperature, while the current gain degradation and temperature-dependent intrinsic density are responsible for increasing the BiCMOS gate pull-down delay at low temperature. The analytical equations provide evaluation of the sensitivity of process and device parameters to circuit performance at different temperatures. Computer simulation of a BiNMOS driver using the present analysis is compared with a PISCES simulation in support of the physical reasoning.

    Journal Title

    International Journal of Electronics

    Volume

    76

    Issue/Number

    2

    Publication Date

    1-1-1995

    Document Type

    Article

    Language

    English

    First Page

    221

    Last Page

    232

    WOS Identifier

    WOS:A1994MX99600004

    ISSN

    0020-7217

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