High-Speed Parallel Vlsi Architectures For Image Decorrelation

    Authors

    T. Acharya;A. Mukherjee

    Comments

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    Abbreviated Journal Title

    Int. J. Pattern Recognit. Artif. Intll.

    Keywords

    CODEC; COMPRESSION; DECOMPRESSION; DECORRELATION; JPEG; PARALLEL; ARCHITECTURE; PREDICTIVE CODING; VLSI; COMPRESSION; Computer Science, Artificial Intelligence

    Abstract

    We present a new high speed parallel architecture and its VLSI implementation to design a special purpose hardware for real-time lossless image compression/decompression using a decorrelation scheme. The proposed architecture can easily be implemented using state-of-the-art VLSI technology. The hardware yields a high compression rate. A prototype 1-micron VLSI chip based on this architectural idea has been designed. The scheme is favourably comparable to the lossless JPEG standard image compression schemes. We also discuss the parallelization issues of the lossless JPEG standard still compression schemes and their difficulties.

    Journal Title

    International Journal of Pattern Recognition and Artificial Intelligence

    Volume

    9

    Issue/Number

    2

    Publication Date

    1-1-1995

    Document Type

    Article

    Language

    English

    First Page

    343

    Last Page

    365

    WOS Identifier

    WOS:A1995RK06200008

    ISSN

    0218-0014

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