Designing High-Performance Processors Using Real Address Prediction

    Authors

    K. A. Hua; L. S. Liu;J. K. Peir

    Comments

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    Abbreviated Journal Title

    IEEE Trans. Comput.

    Keywords

    Address Prediction; Address Translation; Cache; Pipelined Processor; Synonym; Computer Science, Hardware & Architecture; Engineering, Electrical &; Electronic

    Abstract

    In this correspondence, we propose design techniques that may significantly simplify the cache access path, and hence offer the opportunity of shorter cycle time or fewer pipeline stages. Our proposals are based on highly accurate prediction methods that allow us to efficiently resolve address translation information early in the pipe.

    Journal Title

    Ieee Transactions on Computers

    Volume

    42

    Issue/Number

    9

    Publication Date

    1-1-1993

    Document Type

    Note

    Language

    English

    First Page

    1146

    Last Page

    1151

    WOS Identifier

    WOS:A1993MM22000013

    ISSN

    0018-9340

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