Title

A multilayer framework supporting autonomous run-time partial reconfiguration

Authors

Authors

H. Tan;R. F. DeMara

Comments

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Abbreviated Journal Title

IEEE Trans. Very Large Scale Integr.

Keywords

bitstream manipulation; field-programmable gate-array (FPGA) area; management; FPGA run-time environments; frame-based partial; reconfiguration; module-based partial reconfiguration; Computer Science, Hardware & Architecture; Engineering, Electrical &; Electronic

Abstract

A multilayer run-time reconfiguration architecture (MRRA) is developed for autonomous run-time partial reconfiguration of field-programmable gate-array (FPGA) devices. MRRA operations are partitioned into logic, translation, and reconfiguration layers along with a standardized set of application programming interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. In particular, FPGA configurations can be manipulated at runtime using on-chip resources. A corresponding logic control flow is developed for a prototype MRRA system on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Evaluations of these prototypes on a number of benchmark and hashing algorithm case studies indicate the enhanced resource utilization and run time performance of the developed approaches.

Journal Title

Ieee Transactions on Very Large Scale Integration (Vlsi) Systems

Volume

16

Issue/Number

5

Publication Date

1-1-2008

Document Type

Article

Language

English

First Page

504

Last Page

516

WOS Identifier

WOS:000258762700002

ISSN

1063-8210

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