Title

Window-Masked Segmented Digital Clock Manager-FPGA-Based Digital Pulsewidth Modulator Technique

Authors

Authors

M. G. Batarseh; W. Al-Hoor; L. Huang; C. Iannello;I. Batarseh

Comments

Authors: contact us about adding a copy of your work at STARS@ucf.edu

Abbreviated Journal Title

IEEE Trans. Power Electron.

Keywords

DC-DC converters; digital control; digital power electronics; digital; pulsewidth modulators (DPWM); field programmable gate arrays; DC CONVERTERS; IMPLEMENTATION; RESOLUTION; Engineering, Electrical & Electronic

Abstract

This paper presents a new digital pulsewidth modulator (DPWM) architecture for field programmable gate array (FPGA)-based systems. The design of the proposed DPWM architecture is based on fully utilizing the digital clock manager (DCM) resources available on new FPGA boards. Furthermore, this architecture will also window-mask the DCM operation to only a portion of the switching period in order to decrease power dissipation. This proposed digital modulator technique allows for higher DPWM resolution with lower power consumption, the primary barrier to high switching frequency operation. The presented technique relies on power-optimized resources already existing on new FPGAs, and benefits from the inherit phase-shifting properties of the DCM blocks, which help in simplifying the duty cycle generation. The architecture can be applied to achieve different numbers of bits for the DPWM resolution designed for different dc-dc applications. The suggested architecture is first simulated, implemented, and experimentally verified on a Virtex-4 FPGA board.

Journal Title

Ieee Transactions on Power Electronics

Volume

24

Issue/Number

11

Publication Date

1-1-2009

Document Type

Article

Language

English

First Page

2649

Last Page

2660

WOS Identifier

WOS:000273135400001

ISSN

0885-8993

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