Efficient VLSI Architecture for Video Transcoding

    Authors

    J. Huang;J. Lee

    Comments

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    Abbreviated Journal Title

    IEEE Trans. Consum. Electron.

    Keywords

    Video transcoding; unified architecture; motion estimation and; compensation; DCT and IDCT; MATCHING MOTION ESTIMATION; TRANSFORM DOMAIN; DCT-DOMAIN; COMPENSATION; MPEG-2; IMPLEMENTATION; INVERSE; Engineering, Electrical & Electronic; Telecommunications

    Abstract

    In this paper, we present a unified architecture that can perform Discrete Cosine Tran form (DCT), Inverse Discrete Cosine Transform (IDCT), DCT domain motion estimation and compensation (DCT-ME/MC). Our proposed architecture is a Wavefront Array-based Processor with a highly modular structure consisting of 8x8 Processing Elements (PEs). By utilizing statistical properties and arithmetic operations, it can be used as a high performance hardware accelerator for video transcoding applications. We show how different core algorithms can be mapped onto the same hardware fabric and can be executed through the pre-defined PEs. In addition to the simplified design process of the proposed architecture and savings of the hardware resources, we also demonstrate that high throughput rate can be achieved for IDCT and DCT-MC by fully utilizing the sparseness property of DCT coefficient matrix.

    Journal Title

    Ieee Transactions on Consumer Electronics

    Volume

    55

    Issue/Number

    3

    Publication Date

    1-1-2009

    Document Type

    Article

    Language

    English

    First Page

    1462

    Last Page

    1470

    WOS Identifier

    WOS:000270358500071

    ISSN

    0098-3063

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