A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching

    Authors

    J. Huang;J. Lee

    Comments

    Authors: contact us about adding a copy of your work at STARS@ucf.edu

    Abbreviated Journal Title

    IEEE Trans. Circuits Syst. Video Technol.

    Keywords

    Data compression; DCT; FPGA; reconfigurable architectures; video coding; Engineering, Electrical & Electronic

    Abstract

    In this paper, we propose a self-reconfigurable platform which can reconfigure the architecture of discrete cosine transform (DCT) computations during run-time using dynamic partial reconfiguration. The scalable architecture of DCT computations can compute different numbers of DCT coefficients in a zig-zag scan order to adapt to different requirements, such as power consumption, hardware resources, and performance. We propose a configuration manager, which is implemented in the embedded processor in order to adaptively control the reconfiguration of scalable DCT architecture during run-time. In addition, we use the Lempel-Ziv-Storer-Szymanski algorithm for compression of the partial bitstreams and on-chip BlockRAM as a cache to reduce latency overhead for loading the partial bitstreams from the off-chip memory for run-time reconfiguration. A hardware module is designed for parallel reconfiguration of the partial bitstreams. The experimental results show that our approach can reduce the external memory accesses by 69% and can achieve a 400 MB/s reconfiguration rate. Detailed trade-offs of power, throughput, and quality are investigated, and used as a criterion for self-reconfiguration.

    Journal Title

    Ieee Transactions on Circuits and Systems for Video Technology

    Volume

    19

    Issue/Number

    11

    Publication Date

    1-1-2009

    Document Type

    Article

    Language

    English

    First Page

    1623

    Last Page

    1632

    WOS Identifier

    WOS:000271600200006

    ISSN

    1051-8215

    Share

    COinS