Parallel hardware-software architecture for computation of Discrete Wavelet Transform using the Recursive Merge Filtering algorithm

    Authors

    P. Jamkhandi; A. Mukherjee; K. Mukherjee;R. Franceschini

    Keywords

    Computer Science, Theory & Methods

    Abstract

    We present an FPGA-based parallel hardware-software architecture for the computation of the Discrete Wavelet Transform (DWT), using the Recursive Merge Filtering (RMF) algorithm. The DWT is built in a bottom-up fashion in logN steps, successively building complete DWTs by "merging" two smaller DWTs and applying the wavelet filter to only the "smooth" or DC coefficient from the smaller DWTs. The main bottleneck of this algorithm is the data routing process, which can be reduced by separating the computations into two types to introduce parallelism. This is achieved by using a virtual mapping structure to map the input. The data routing bottleneck has been transformed into simple arithmetic computations on the mapping structure. Due to the use of the FPGA-RAM for the mapping structure, the total number of data accesses to the main memory are reduced. This architecture shows how data routing in this problem can be transformed into a series of index computations.

    Journal Title

    Parallel and Distributed Processing, Proceedings

    Volume

    1800

    Publication Date

    1-1-2000

    Document Type

    Article

    Language

    English

    First Page

    250

    Last Page

    256

    WOS Identifier

    WOS:000171729800030

    ISSN

    0302-9743; 3-540-67442-X

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