Performance of scalable shared-memory architectures

    Authors

    B. S. Motlagh;R. F. DeMara

    Comments

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    Abbreviated Journal Title

    J. Circuits Syst. Comput.

    Keywords

    Computer Science, Hardware & Architecture; Engineering, Electrical &; Electronic

    Abstract

    Analytical models were developed and simulations of memory latency were performed for Uniform Memory Access (UMA), Non-Uniform Memory Access (NUMA), Local-Remote-Global (LRG), and RCR architectures for hit rates from 0.1 to 0.9 in steps of 0.1, memory access times of 10 to 100 ns, proportions of read/write access from 0.01 to 0.1, and block sizes of 8 to 64 words. The RCR architecture provides favorable performance over UMA and NUMA architectures for all ranges of application and system parameters. RCR outperforms LRG architectures when the hit rates of the processor cache exceed 80% and replicated memory exceed 25%. Thus, inclusion of a small replicated memory at each processor significantly reduces expected access time since all replicated memory hits become independent of global traffic. For configurations of up to 32 processors, results show that latency is further reduced by distinguishing burst-mode transfers between isolated memory accesses and those which are incrementally outside the working set.

    Journal Title

    Journal of Circuits Systems and Computers

    Volume

    10

    Issue/Number

    1-2

    Publication Date

    1-1-2000

    Document Type

    Article

    Language

    English

    First Page

    1

    Last Page

    22

    WOS Identifier

    WOS:000090137700001

    ISSN

    0218-1266

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