Design optimization of stacked layer dielectrics for minimum gate leakage currents

    Authors

    J. Zhang; J. S. Yuan; Y. Ma;A. S. Oates

    Abbreviated Journal Title

    Solid-State Electron.

    Keywords

    Engineering, Electrical & Electronic; Physics, Applied; Physics, ; Condensed Matter

    Abstract

    An effective model to evaluate the leakage currents for different stacked gates deep submicron MOS transistors is presented. For a given equivalent oxide thickness of a stacked gate, the gate leakage current decreases with an increase of high-k dielectric thickness or a decrease of interlayer thickness. Turning points at high gate biases of the I-V curves are observed for Si3N4SiO2, Ta2O5/SiO2, Ta2O5/SiO2-yNy, Ta2O5/Si3N4, and TiO2/SiO2 stacked gates except for Al2O3/SiO2 structure, Design optimization fur the stacked gate architecture to obtain the minimum gate leakage current is evaluated. (C) 2000 Elsevier Science Ltd. All rights reserved.

    Journal Title

    Solid-State Electronics

    Volume

    44

    Issue/Number

    12

    Publication Date

    1-1-2000

    Document Type

    Article

    Language

    English

    First Page

    2165

    Last Page

    2170

    WOS Identifier

    WOS:000166666000011

    ISSN

    0038-1101

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