Title

SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests

Authors

Authors

Q. Zhang; J. J. Liou; J. R. McMacken; J. Thomson;P. Layman

Comments

Authors: contact us about adding a copy of your work at STARS@ucf.edu

Abbreviated Journal Title

IEEE J. Solid-State Circuit

Keywords

analog circuits; BSIM3v3 model; statistical circuit simulation; transistor mismatch; TRANSISTORS; Engineering, Electrical & Electronic

Abstract

This paper reports a MOS transistor mismatch model applicable for submicron CMOS technologies and developed based on the industry standard BSIM3v3 model. A simple and unified expression was derived to formulate the effect of MOSFET mismatch on drain current variance. A way to quickly estimate the drain current mismatch was also suggested. The model has been integrated into HSPICE, and results obtained from simulation and measurements were compared.

Journal Title

Ieee Journal of Solid-State Circuits

Volume

36

Issue/Number

10

Publication Date

1-1-2001

Document Type

Article

Language

English

First Page

1592

Last Page

1595

WOS Identifier

WOS:000171192400020

ISSN

0018-9200

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