Title

Routing on field-programmable switch matrices

Authors

Authors

A. Ejnioui;N. Ranganathan

Abbreviated Journal Title

IEEE Trans. Very Large Scale Integr.

Keywords

field programmable gate arrays (FPGAs); interconnect structures; multi-FPGA systems; switch routing; Computer Science, Hardware & Architecture; Engineering, Electrical &; Electronic

Abstract

In this paper, we address the problem of routing nets on field programmable gate arrays (FPGAs) interconnected by a switch, matrix. We extend the switch matrix architecture proposed by Zhu et al. to route nets between FPGA chips in a multi-FPGA system. Given a limited number of routing resources in the form of programmable connection points within a two-dimensional switch matrix, this problem examines the issue of how to route. a given net traffic through the switch matrix structure. First, we define the problem as a general undirected graph in which each vertex has one single color among six possible colors and formulate it as a constraint satisfaction problem. This is further modeled as a 0-1 multidimensional knapsack Problem for Which a fast approximate solution is applied. Experimental results show that the accuracy of our Proposed heuristic is quite high for moderately large switch matrices.

Journal Title

Ieee Transactions on Very Large Scale Integration (Vlsi) Systems

Volume

11

Issue/Number

2

Publication Date

1-1-2003

Document Type

Article

Language

English

First Page

283

Last Page

287

WOS Identifier

WOS:000184091000013

ISSN

1063-8210

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