Optimization of on-chip ESD protection structures for minimal parasitic capacitance

    Authors

    X. F. Gao; J. J. Liou; J. Bernier; G. Croft; W. Wong;S. Vishwanathan

    Abbreviated Journal Title

    Microelectron. Reliab.

    Keywords

    Engineering, Electrical & Electronic; Nanoscience & Nanotechnology; Physics, Applied

    Abstract

    Diodes are key components in on-chip electrostatic discharge (ESD) protection design. As the operating frequency of the microchip being protected against the ESD continues to increase, the parasitic capacitance associated with the diodes in the ESD structure starts to impose problems for RF operation. This paper presents a systematic approach to optimize the diode structure for minimal parasitic capacitance based on the requirements of breakdown. voltage and heat dissipation. Device simulator Atlas with mix-mode simulation capability is calibrated against measurement data and used to carry out the optimization. An optimized diode structure with a parasitic capacitance of less than 30 fF at an operating frequency of 10 GHz and ESD charging voltage of I kV has been suggested. Furthermore, a case study to implement and optimize the ESD protection structure based on an existing 0.13-mum CMOS technology has been presented and verified. (C) 2003 Elsevier Science Ltd. All rights reserved.

    Journal Title

    Microelectronics Reliability

    Volume

    43

    Issue/Number

    5

    Publication Date

    1-1-2003

    Document Type

    Article

    Language

    English

    First Page

    725

    Last Page

    733

    WOS Identifier

    WOS:000182966900005

    ISSN

    0026-2714

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