A genetic representation for evolutionary fault recovery in virtex FPGAs

    Authors

    J. Lohn; G. Larchev;R. DeMara

    Comments

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    Keywords

    Computer Science, Artificial Intelligence; Computer Science, Hardware &; Architecture; Computer Science, Theory & Methods

    Abstract

    Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of transistors in a typical FPGA are dedicated to interconnect, nearly 80% according to one estimate, evolutionary fault-recovery systems should benefit by accommodating routing. In this paper, we propose an evolutionary fault-recovery system employing a genetic representation that takes into account both logic and routing configurations. Experiments were run using a software model of the Xilinx Virtex FPGA. We report that using four Virtex combinational logic blocks, we were able to evolve a 100% accurate quadrature decoder finite state machine in the presence of a stuck-at-zero fault.

    Journal Title

    Evolvable Systems: From Biology to Hardware, Proceedings

    Volume

    2606

    Publication Date

    1-1-2003

    Document Type

    Article

    Language

    English

    First Page

    47

    Last Page

    56

    WOS Identifier

    WOS:000182975200005

    ISSN

    0302-9743; 3-540-00730-X

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