Modelling and analysis of ground bounce due to internal gate switching

    Authors

    L. Yang;J. S. Yuan

    Comments

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    Abbreviated Journal Title

    IEE Proc.-Circuit Device Syst.

    Keywords

    SIGNAL INTEGRATED-CIRCUITS; NOISE; DESIGN; LOGIC; Engineering, Electrical & Electronic

    Abstract

    Ground bounce noise due to internal gate switching is studied. Unlike the ground bounce caused by switching of the output buffer, both power-rail and ground-rail impedances are important, and a double negative feedback mechanism must be considered. Based on the lumped-model analysis and taking into account the parasitic and velocity-saturation effects of MOS transistors, an analytical model is developed including both switching and non-switching gates. The proposed model is employed to analyse the on-chip decoupling capacitance, resonant frequency, wire/pin inductance and loading effect. Good agreement between the model predictions and SPICE simulation results is obtained.

    Journal Title

    Iee Proceedings-Circuits Devices and Systems

    Volume

    151

    Issue/Number

    4

    Publication Date

    1-1-2004

    Document Type

    Article

    Language

    English

    First Page

    300

    Last Page

    306

    WOS Identifier

    WOS:000224250100005

    ISSN

    1350-2409

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